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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-21349-1E
ASSP
Single Serial Input PLL Frequency Synthesizer
On-Chip prescaler
MB15C03
s DESCRIPTION
The Fujitsu MB15C03 is a serial input Phase Locked Loop (PLL) frequency synthesizer with a prescaler. A 64/ 65 division is available for the prescaler that enables pulse swallow operation. This operates with a supply voltage of 1.0 V (min.). MB15C03 is suitable for mobile communications, such as paging systems.
s FEATURES
* Frequency operation * Separate power supply : * * * * 90 MHz @VDD = 1.0 to 1.5V 120 MHz @VDD = 1.2 to 1.5V VDD = 1.0 to 1.5 V (for overall system) VP = 2.0V to 3.5V (for a charge pump)
Power saving function Pulse swallow function: 64/65 Serial input 14-bit programmable reference divider: R = 5 to 16,383 Serial input 18-bit programmable divider consisting of: - Binary 6-bit swallow counter: 0 to 63 - Binary 12-bit programmable counter: 5 to 4,095 * Wide operating temperature: Ta = -20 to +60C * Plastic 16-pin SSOP package (FPT-16P-M05)
s PACKAGE
16-pin, plastic SSOP
(FPT-16P-M05)
This device contains circuitry to protect the inputs against damage due to high static voltages or electroc fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
MB15C03
s PIN ASSIGNMENT
VDD
Clock Data LE fin PS LD DO
1 2 3 4
16 15 14
VSS OSCIN OSCOUT TEST FC fp fr VP
TOP 13 VIEW 5 12 6 7 8 11 10 9
2
MB15C03
s PIN DESCRIPTIONS
Pin no. 1 2 3 4 Pin name VDD Clock Data LE I/O -- I I I System 1V 1V 1V 1V Power supply voltage Clock input for the shift register. Data is shifted into the shift register on the rising edge of the clock. Serial data input using binary code. Load enable signal input When LE is high, the data in the shift register is transferred to a latch, according to the control bit in the serial data. Prescaler input. A bias circuit and amplifier are at input port. Connection with an external VCO should be done by AC coupling. Power saving mode control. This pin must be set at "L" at Power-ON. PS = "H" ; Normal mode PS = "L" ; Power saving mode Lock detector signal output. When a PLL is locking, LD outputs "H". When a PLL is not locking, LD outputs "L". Charge pump output. Phase of the charge pump can be reversed by FC input. The DO output may be inverted by FC input. The relationships between the programmable reference divider output(fr) and the programmable divider output(fp) are shown below; fr > fp : "H" level (FC= "L"), "L" level (FC= "H") fr = fp : High impedance fr < fp : "L" level (FC= "L"), "H" level (FC= "H") Power supply for the charge pump. Programmable reference counter output (fr) monitoring pin. Programmable counter output (fp) monitoring pin. Phase comparator input select pin. Test mode select pin. (Pull down resistor) Setting this pin to "H", test mode becomes available. Please set this pin to ground or open usually. Oscillator output. Connection for an external crystal. Programmable reference divider input. Oscillator input. Clock can be input to OSCIN from outside. In the case, please leave OSCOUT pin open and make connection with OSCIN as AC coupling. Ground. Descriptions
5
fin
I
1V
6
PS
I
1V
7
LD
O
1V
8
DO
O
3V
9 10 11 12 13 14
VP fr fp FC TEST OSCOUT
-- O O I I O
3V 1V 1V 1V 1V 1V
15 16
OSCIN VSS
I --
1V --
3
MB15C03
s BLOCK DIAGRAM
VDD
1
Programmable reference divider
Binary 14-bit reference counter
Crystal Oscillator circuit fr
16 VSS
15 OSCIN
Intermittent mode control circuit
14 OSCOUT
14
fr 14-bit latch
Clock 2
13 TEST
Phase comparator fp
12 FC
14
11
fp
Data 3
Control register
18-bit shift register
10
fr
18
LE
4
18-bit latch
6
12
fin 5 PS
6
Prescaler
Binary 6-bit swallow counter
Binary 12-bit programmable counter
fp
Charge pump
9
VP
LD
7
Lock detector
Control Circuit
Do 8
4
MB15C03
s ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Output voltage Output current Operating temperature Storage temperature Symbol VDD VP VIN VOUT VOUTP IOUT Ta Tstg Rating Min. GND -0.5 GND -0.5 GND -0.5 GND -0.5 GND -0.5 -10 -20 -40 Max. +2.0 +5.0 VDD +0.5 VDD +0.5 VP +0.5 +10 +60 +125 Unit V V V V V mA C C Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Symbol VDD VP Input voltage Operating temperature VIN Ta Value Min. 1.0 1.2 2.0 GND -20 Typ. -- -- -- -- -- Max. 1.5 1.5 3.5 VDD +60 Unit V V V C Remark For 90 MHz For 120 MHz
Power supply voltage
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.
HandIing Precautions
* This device should be transported and stores in anti-static containers. * This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats. * Always turn the power supply off before inserting or removing the device from its socket. * Protect leads with a conductive sheet when handling or transporting PC boards with devices.
5
MB15C03
s ELECTRICAL CHARACTERISTICS
(For 90 MHz: VDD = 1.0 V to 1.5 V, VP = 2.0 V to 3.5 V, Ta = -20C to +60C) (For 120 MHz: VDD = 1.2 V to 1.5 V, VP = 2.0 V to 3.5 V, Ta = -20C to +60C) Value Symbol Condition Unit *3 Min. Typ.*4 Max. Active Mode IDD*1 (VDD = 1.0 V/ 90 MHz) (VDD = 1.2 V/ 120 MHz) (VDD = 1.0 V) (VDD = 1.2 V) (VDD = 1.0 V to 1.5 V) (VDD = 1.2 V to 1.5 V) -- -- -- -- -- VIN = VDD VIN = GND IOH = -0.3 mA IOL = 0.3 mA IOHP = -1.0 mA IOLP = 1.0 mA VOUT = GND to VP -- -- -- -- 10 10 5 -4.0 -4.0 VDD - 0.2 - - -1.0 VDD - 0.2 - VP - 0.2 - -100 0.5 0.7 10 15 -- -- - - - - - - - - - - - - 1.0 1.4 100 120 90 120 20 - - - 0.2 +1.0 - - 0.2 - 0.2 100 nA V A mA A MHz MHz dBm dBm V
Parameter Supply current Power saving current
Power saving IDDS*2 mode fin OSCIN fin fOSC Vfin VOSC "H" level "L" level "H" level "L" level "H" level "L" level "H" level "L" level VIH VIL IIH IIL VOH VOL VOHP VOLP Ioff
Operating frequency fin OSCIN Except for fin and OSCIN Except for fin, OSCIN and TEST Except for OSCOUT Output voltage DO High impedance DO cutoff current
Input sensitivity
Input voltage
Input current
V
*1: Conditions; fin = 90MHz or 120MHz, 16.0MHz crystal between OSCIN and OSCOUT, Inputs except for fin, OSCIN and TEST are grounded, Outputs are opened. *2: Conditions; PS = Low, Inputs are grounded except for fin, OSCIN and TEST. Outputs are opened. *3: Condition; Ta = 25C *4: Condition; Ta = -20C to +60C
6
MB15C03
s FUNCTIONAL DESCRIPTIONS
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation: fVCO = [(M x N) + A] x fOSC / R (A < N) fVCO : Output frequency of external voltage controlled oscillator (VCO) N : Preset divide ratio of binary 12-bit programmable counter (5 to 4,095) A : Preset divide ratio of binary 6-bit swallow counter (0 to 63) fOSC : Output frequency of the reference frequency oscillator R : Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383) M : Preset modulus of dual modulus prescaler (64)
2. Circuit Description (1) Intermittent operation
The intermittent operation of the MB15C03 refers to the process of activating and deactivating its internal circuit thus saving power dissipation otherwise consumed by the circuit. If the circuit is simply restarted from the power saving state, however, the phase relation between the reference frequency (fr) and the programmable frequency (fp), which are the input to the phase comparator, is not stable even when they are of the same value. This may cause the phase comparator to generate an excessively large error signal, resulting in an out-of-synth lock frequency. To preclude the occurrence of this problem, the MB15C03 has an intermittent mode control circuit which forces the frequencies into phase with each other when the IC is reactivated, thus minimizing the error signal and resultant lock frequency fluctuations. The intermittent mode control circuit is controlled by the PS pin. Setting pin PS high provides the normal operation mode and setting the pin low provides the power saving mode. The MB15C03 behavior in the active and power saving modes is summarized below. Active mode (PS = "H") All MB15C03 circuits are active and provide the normal operation. Power saving mode (PS = "L") The MB15C03 stops any circuits that consume power heavily as well as cause little inconvenience when deactivated and enters the low-power dissipation state. DO and LD pins take the same state as when the PLL is locked. DO pin becomes a high-impedance state. Applying the intermittent operation by alternating the active and power saving modes, and also forcing the phases of fr and fp to synchronize when it switches from stand by to active modes, the MB15C03 can keep the power dissipation of its entire circuitry to the minimum.
7
MB15C03
(2) Programmable divider
The fvco input through fin pin is divided by the programmable divider and then output to the phase comparator as fp. It consists of a dual modulus prescaler, a 6-bit binary swallow counter, a 12-bit binary programmable counter, and a controller which controls the divide ratio of the prescaler. Divide ratio range: Prescaler : M = 64, M + 1 = 65 Swallow counter : A = 0 to 63 Programmable counter : N = 5 to 4095 The MB15C03 uses the pulse swallow method; consequently, the divide rations of the swallow and programmable counters must satisfy the relationship N > A. The total divide ratio of the programmable divider is calculated as follows: Total divide ratio = (M+1) x A + M x (N-A) = M x N + A = 64 x N + A When N is set within 564 must be satisfied for the total divider to be set within 0(3) Programmable reference divider
The programmable reference divider divides the reference oscillation frequency (fosc) from the crystal oscillator connected between OSCIN and OSCOUT pins or from the external oscillator input taken in directly through OSCIN, pin and then, sends the resultant fr to the phase comparator. It consists of a 14-bit binary programmable reference counter. When the output from the external oscillator is to be input directly to OSCIN pin, the connection must be AC coupled and OSCOUT pin is left open. Also, to prevent OSCOUT from malfunctioning, its traces on the printed circuit board must be kept minimal or eliminated entirely; whenever possible, it must be free of any form of load. The following divider is used: Programmable reference counter : R = 5 to 16383 The fr and fosc have the following relation: fr = fosc / R
(4) Phase comparator
The phase comparator detects the phase difference between the outputs fr and fp from the dividers and generates an error signal that is proportional to phase difference. The outputs from the phase comparator include DO which takes on one of the three states, namely, "L" (low), "H" (high), and "Z" (high impedance), and is sent to the LPF LD which indicates the PLL lock or unlock states. (a) Phase comparator The phase comparator detects the phase error between fr and fp, then generates an error signal that is proportional to the phase error. The roles of the fr and fp supplied to the phase comparator may be reversed by switching the logical input level of pin FC. This inverts the logical level of the DO output. The logical level of DO output may be selected according to the characteristics of the external LPF and the VCO. (Refer to Table 1.)
8
MB15C03
Table.1 Phass comparator inputs/output relationships FC fr > fp fr = fp fr < fp "L" H Z L "H" L Z H
(b) Phase comparator input/output waveforms The phase comparator outputs logic levels summarized in Table 1, according to the phase error between fr and fp. The pulse width of the phase comparator outputs are identical and equal to the phase error between fr and fp as shown in Figure 1.
Figure 1 Phase comparator input/output waveforms
fr
fp
When FC = "L"
DO
High Z
When FC = "H"
DO
High Z
High Z : High impedance state
9
MB15C03
(c) Lock detector The lock detector detects the lock and unlock states of the PLL. The lock detector outputs "H" when the PLL enters the lock state and outputs "L" when the PLL enters the unlock state as shown in Figure 2. When PS = "L", the lock detector outputs "H" compulsorily.
Figure 2 Phase comparator input/output waveforms (lock detector)
fr
fp
LD
10
MB15C03
3. Setting the Divide Ratio (1) Serial data format
The format of the serial data is shown is Figure 3. The serial data is composed of control bits and divide ratio setting data. The contorl bits select the programmable divider or programmable reference divider. In case of the programmable divider, serial data consists of 18 bits (6 bits for the swallow counter and 12 bits for the programmable counter) and control bits as shown in Figure 3.1. In case of the programmable reference divider, the serial data consists of 14 bits and 2 control bits as shown in Figure 3.2. The control bits are set to: C0 = C1= 0 C0 = 0, C1 = 1 for the programmable divider for the programmable reference divider.
Figure 3 Serial data format
LSB Direction of data input MSB
C 0
C 1
A 0
A 1
A 2
A 3
A 4
A 5
N 0
N 1
N 2
N 3
N 4
N 5
N 6
N 7
N 8
N 9
10
N
11
N
(=0) (=0) Swallow counter Control bit Programmable counter
Figure 3.1 Divide ratio for the programmable divider
LSB Direction of data input
MSB
C 0
C 1
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
R 8
R 9
10
R
11
R
12
R
13
R
(=0) (=1) Programmable reference counter Control bit
Figure 3.2 Divide ratio for the programmable reference divider
(2) The flow of serial data
Serial data is received via data pin in synchronization with the clock input and loaded into shift register which contains the divide ratio setting data and into the control register which contains the control bit. The logical product (through the AND gate in Figure 4) of LE and the control register output (i.e., control bit) is fed to the enable input of the latches. Accordingly, when LE is set high, the latch for the divider identitied by the control bit is enabled and the divide ratio data from the shift register is loaded into the selected counter(s).
11
MB15C03
Figure 4 The flow of serial data
14-bit binary programmable reference counter
Programmable reference divider
14 AND
14-bit latch
14
Data C* Clock LE AND 18
18-bit shift register
18-bit latch
6 Prescaler
12 Programmable divider
6-bit binary swallow counter 12-bit binary programmable counter
* : Control register
(3) Setting the divide ratio for the programmable divider
Columns A0 to A5 of Table.2.1 represent the divide ratio of the swallow counter and columns N0 to N11 of Table.2.2 represent the divide ratio of programmable counter. The control bit is set to 0. Table. 2 Divide ratio for the programmable divider Table.2.1 Swallow counter divider A Divide ratio (A) 0 1 * 63 A 0 0 1 * 1 A 1 0 0 * 1 A 2 0 0 * 1 A 3 0 0 * 1 A 4 0 0 * 1 A 5 0 0 * 1 Divide ratio (N) 5 6 * 4095 Table.2.2 Programmable counter divider N N 0 1 0 * 1 N 1 0 1 * 1 N 2 1 1 * 1 N 3 0 0 * 1 N 4 0 0 * 1 N 5 0 0 * 1 N 6 0 0 * 1 N 7 0 0 * 1 N 8 0 0 * 1 N 9 0 0 * 1 N 10 0 0 * 1 N 11 0 0 * 1
Note: Less than 5 is prohibited. 12
MB15C03
(4) Setting the divide ratio for the programmable reference divider
Columns R0-R13 of Table 3 represent the divide ratio of the programmable reference counter. The control bit is set to 1. Table.3 Divide ratio for the programmable reference divider Divide ratio (R) 5 6 * 16383 R 0 1 0 * 1 R 1 0 1 * 1 R 2 1 1 * 1 R 3 0 0 * 1 R 4 0 0 * 1 R 5 0 0 * 1 R 6 0 0 * 1 R 7 0 0 * 1 R 8 0 0 * 1 R 9 0 0 * 1 R 10 0 0 * 1 R 11 0 0 * 1 R 12 0 0 * 1 R 13 0 0 * 1
Note: Less than 5 is prohibited.
(5) Setting data input timing
The MB15C03 uses 20 bits of serial data for the programmable divider and 16 bits for the programmable reference divider. When more bits of serial data than defined for the target divider are received, only the last valid serial data bits are effective. To set the divide ratio for the MB15C03 dividers, it is necessary to supply the Data, Clock, and LE signals at the timing shown in Figure 5. t1 ( 0.5 s): Data setup time t2 ( 0 5 s): Data hold time t3 ( 0.5 s): Clock pulse width t5 ( 0.5 s): LE pulse width
t4 ( 0.5 s): LE setup time to the rising edge of last clock
13
MB15C03
Figure 5 Serial data input timing
Data
Clock
LE t2 t1 t3 t4 t5
Since the divide rations are unpredictable when the MB15C03 is turned on, it is necessary to initialize the divide ratio for both dividers at power-on time. As shown in Figure 6, after setting the divide ratio for one of the dividers (e.g., programmable reference divider), set LE to "H" level before setting the divide ratio for the other divider (e.g., programmable divider). To change the divide ratio of one of the dividers after initialization, input the serial data only for that divider (the divide ratio for the other divider is preserved). Figure 6 Inputting serial data (Setting divisors)
Data
Serial data for programmable reference divider
C
Serial data for programmable divider
C
16 clocks Clock
20 clocks
LE * : Control bit(2 bits)
14
MB15C03
s TYPICAL CHARACTERISTIC CURVES
1. fin Input Sensitivity Characteristics
fin input frequency vs. Input sensitivity
0.0 Ta = +25C
-10.0
Input sensitivity (dBm)
-20.0
-30.0
-40.0 VDD = 1.0 V VDD = 1.2 V VDD = 1.5 V
-50.0
-60.0 0 100 200 300 400 500 600 700 800 900 1000 fin input frequency (MHz)
2. OSCIN Input Sensitivity Characteristics
OSCIN input frequency vs. Input sensitivity
0.0 Ta = +25C
-10.0
Input sensitivity (dBm)
-20.0
-30.0
-40.0 VDD = 1.0 V VDD = 1.2 V VDD = 1.5 V
-50.0
-60.0 0 50 100 150 200 250 300 350 400 450 500 OSCIN input frequency (MHz)
15
MB15C03
3. fin Power Supply Voltage Dependency
Power supply voltage vs. fin input frequency
1000 Vfin = -4.0 (dBm) 900 800 700 600 500 400 300 200 100 0 0.9 Ta = +25C
fin input frequency (MHz)
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Power supply voltage (V)
4. OSCIN Power Supply Voltage Dependency
Power supply voltage vs. OSCIN input frequency
500 Vfin = -4.0 (dBm) 450 400 OSCIN input frequecy (MHz) 350 300 250 200 150 100 50 0 0.9 Ta = +25C
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Power supply voltage (V)
16
MB15C03
5. Power Supply Current Characteristics
fin input frequency vs. Power supply current
5.0 Ta = +25C 4.5 4.0 3.5 Power supply current (mA) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 100 200 300 400 500 600 700 800 900 1000 fin input frequecy (MHz) VDD = 1.0 V VDD = 1.2 V VDD = 1.5 V
Power supply voltage vs. Power supply current
5.0 Ta = +25C 4.5 4.0 3.5 Power supply current (mA) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.9 fin = 90 (MHz) fin = 120 (MHz) Vfin = -4.0 (dBm)
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Power supply voltage (V)
17
MB15C03
6. IDD (Lock) Power Supply Voltage Dependency
VDD -- IDD
1.6 Ta = +25C 1.4 1.2 1.0 IDD (mA) 0.8 0.6 0.4 0.2 0.0 0.9 1.0 1.1 1.2 1.3 1.4 VDD (V) 1.5 1.6 1.7 1.8 fvco = 50 MHz fvco = 130 MHz
VDD MB15C03 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
VCO 1000 p
1000 p 50 SG OSCIN = 16.0 MHz (0.4 VP - P)
50
VP
LPF
18
MB15C03
7. DO (Chargepump) Power Supply Voltage Dependency
IOL (DO) -- VOL (DO)
3.5 VP = 3.0 V, Ta = +25C 3.0 2.5 VOL (V) 2.0 1.5 1.0 0.5 0.0 0 2 4 6 8 10 IOL (mA) 12 14 16 18 20
IOH (DO) -- VOH (DO)
3.5 VP = 3.0 V, Ta = +25C 3.0 2.5 VOH (V) 2.0 1.5 1.0 0.5 0.0 0 -2 -4 -6 -8 -10 IOH (mA) -12 -14 -16 -18 -20
19
MB15C03
8. Spectrum Waveforms
ATTEN 10 dB RL 0 dBm UAUG 0 10 dB/ MKR -84.50 dB 25.0 kHz * LOCK Frequency: 130.0 MHz (fr = 25 kHz) * V DD = 1.2 V, V p = 3.0 V Ta = +25C
MKR D 25.0 KHz S -84.50 dB
CENTER 130.0000 MHz * RBW 1.0 kHz UBW 1.0 kHz
SPAN 200.0 kHz * SWP 1.00 s
ATTEN 10 dB RL 0 dBm
UAUG 50 10 dB/
MKR -68.50 dB 1.97 kHz * LOCK Frequency: 130.0 MHz (fr = 25 KHz) * V DD = 1.2 V, V p = 3.0 V Ta = +25C
MKR D 1.97 kHz S -68.50 dB
CENTER 130.00000 MHz * RBW 100 Hz UBW 100 Hz
SPAN 20.00 kHz * SWP 3.00 s
* Mesurement circuit
DO 1.5 k 1.5 k 6800 pF 4700 pF 68000 pF
VT (to VCO)
*VCO : KV = 4.635 MHz/v
20
MB15C03
9. Lock-up Time
* LOCK Frequency: 131.0 MHz to 124.0 MHz (fr = 25 kHz) * V DD = 1.2 V, V P = 3.0 V, Ta = +25C 131.0 MHz 124.0 MHz, within 1 kHz * LOCK Frequency: 124.0 MHz to 131.0 MHz (fr = 25 KHz) * V DD = 1.2 V, V P = 3.0 V, Ta = +25C 124.0 MHz 131.0 MHz, within 1 kHz
3.10 ms
MKr x: 3.10000214 ms y: - 6.99991 MHz 124.0050 MHz A euts N/A MKr x: 3.70000010 ms y: 7.00041 MHz 131.0050 MHz
3.70 ms
A euts N/A
2.00 kHz/div
2.00 kHz/div
123.9950 MHz 0s 10.0000000 ms
130.9950 MHz 0s 10.0000000 ms
* LOCK Frequency: 130.0 MHz (fr = 25 kHz) * V DD = 1.2 V, V P = 3.0 V, Ta = +25C PS ON 130.0 MHz, within 1 kHz
2.20 ms
MKr x: 2.19999981 ms y: 130 Hz 130.0050 MHz A euts N/A
2.00 kHz/div
129.9950 MHz 0 s 8.0000000 ms
PS
1V 0V
21
MB15C03
s ORDERING INFORMATION
Part number MB15C03PFV Package 16-pin, Plastic SSOP (FPT-16P-M05) Remarks
22
MB15C03
s PACKAGE DIMENSION
16-pin, plastic SSOP (FPT-16P-M05)
* 5.000.10(.197.004)
* : These dimensions do not include resin protrusion.
1.25 -0.10 +.008 .049 -.004
+0.20
(Mounting height)
0.10(.004)
INDEX
*4.400.10
(.173.004)
6.400.20 (.252.008)
5.40(.213) NOM
0.650.12 (.0256.0047)
0.22 -0.05 +.004 .009 -.002
+0.10
"A"
0.15 -0.02 +.002 .006 -.001
+0.05
Details of "A" part 0.100.10(.004.004) (STAND OFF)
4.55(.179)REF
0
10
0.500.20 (.020.008)
C
1994 FUJITSU LIMITED F16013S-2C-4
Dimensions in mm (inches)
23
MB15C03
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3753 Fax: (044) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http:.//www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281 0770 Fax: (65) 281 0220
http://www.fmap.com.sg/
F9710 (c) FUJITSU LIMITED
Printed in Japan
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